Ghidra Plugin for Fujitsu FR60 Processors. Focused on DVRP's MB91302A in the Sony PSX.

Overview

Fujitsu FR60 Ghidra Plugin

This repository contains a plugin for Ghidra that enables decompilation support for FR60 processors from Fujitsu. In particular this project targets the MB91302A used in the PlayStation PSX. It includes a loader for the DVRP firmware used in the PSX to help automatically setup memory ranges.

There is no reason why this plugin cannot be used with other processors from this instruction family, however some functionality may be unimplemented, specifically the Co-Processor logic is completely stubbed out in this plugin.

Building

This project requires Gradle 7+ and OpenJDK 11. It has only been tested on Ghidra 10.1.2.

gradle -PGHIDRA_INSTALL_DIR=/path/to/ghidra buildExtension

Installing

Builds are distributed on the RELEASES page. These can be installed directly into Ghidra by selecting File -> Install Extensions from the main Ghidra UI.

The installation includes support for the FR60 instruction set, as well as a file loader that will detect DVRP fimrware and automatically setup the memory space for the firmware by reading the header.

The decompiler will also automatically identify function calls that align with the Fujitsu C/C++ compiler's output, however given hand rolled assembly was commonly used, not all functions will be correctly identified.

There is also an included script, ResolveUTronSyscalls, which will scan the application and identify the standard Fujitsu μTron syscalls, automatically naming these syscalls. The function definition of each syscall is defined in the Fujitsu documentation HERE.

Would be great to have a way to automatically load these function signatures with this script, contributions welcome!

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Comments
  • Program Status, CC flags, and FR81

    Program Status, CC flags, and FR81

    Updated the CC flags to avoid XOR and compare against zero or non-zero to hopefully get better results. Since we have the fake registers for better decompilation, PS should try to sync with them when possible.

    Added three new FR81/FR80 instructions: SRCH0, SRCH1, and SRCHC. The encodings do not conflict with any current instructions

    opened by mumbel 4
  • bug in all conditional branches

    bug in all conditional branches

    I am not familiar with FR60's, I just started playing with it.

    But I found that @mumbel (hi!) made a mistake in his commit.

    All code in CC: table should be rewritten from CC: "RA" is cc=0x0 { local tmp:1 = 1; export *[const]:1 tmp; } to CC: "RA" is cc=0x0 { local tmp:1 = 1; export tmp; }

    Current implementation tries to read memory at address 0 or 1, this is completely wrong.

    opened by esaulenka 3
  • Additional cleanup and improvements

    Additional cleanup and improvements

    • Added comments to each instruction
    • Cleaned up coprocessor instructions
    • Included instructions found in MB91301
    • usignedi_4 and signedi_4 can be handled with "signed" tokens
    • shifted bits instead of multiply
    • Cleaned up +16 bit instructions
    • Carry flag was calculated from register with operation applied twice
    • show store from pcodeop stres

    Bumps ldef version due to instruction decoding changes

    opened by mumbel 3
  • special registers not mapped

    special registers not mapped

    Cannot disassemble b3 00 MOV R0,TBR

    To improve that, please add rs4_4 to this line: https://github.com/desrdev/ghidra-fr60/blob/a8ecd56cc895d88b62a6ea8de8fafbc959245de3/data/languages/fr60.sinc#L71

    opened by esaulenka 0
Releases(v1.2)
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